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jonk
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19 Jan 2008, 11:56 pm

gamefreak wrote:
jonk wrote:
SirLogiC wrote:
I would take it by your long and very technical post that your main interest is computers right

:roll: :P :wink:
Hehe. I spent some time training on the internal design of the P-II CPU at Intel and I did chipset testing for them, for a while. I have designed some cpus, as well. And I enjoy the technology a lot. I also write a lot of software, including operating systems and compilers, though it's been 20 years since I've seriously done the compiler part.

I suppose that's a yes. ;)

Jon


If you designed the Intel P2 why didn`t you guys just put Full-Speed Cache on them like Intel did on the Celeron- 300A+. It cheaper and you get about the same performence comparing 128KB Full-Speed and 512KB Half=Speed Cache.

No, I didn't design it. I was __trained__ on its design. Different thing. I learned about the data flows, registration station, ROB, etc. About how it had already been designed by others.

In terms of cache, I can't tell you why choices were made in specific cases except to suggest that basically most everything comes down to yield/profit. The L1 caches are (were) built on the same die with the CPU. The L2 caches are connected over a separate (or were) back side bus and were on separate dies. Back in the day, anyway. Making the L1 bigger was a huge help in speed, of course, but you paid for it in terms of larger die area which meant lower yield and higher costs, which most customers wouldn't know beans about and would just buy like candy, either way. So why give them something they won't really appreciate and pay for? As shinks occurred, the clock rates increased and the die area descreased, but the smaller feature size meant far tighter control of various parameters in the manufacture. Also, larger wafer sizes give greater yield per wafer, but also lead to great difficulties in keeping uniform temperatures across the wafer during heating which either means longer processing times or better control of the heat mechanisms or else concerns about losing wafers to potato chipping or other defects. Anyway, balancing all these things in various ways, plus market analysis all gets munged together in making decisions. Some of the older CPUs had the largest L1 caches and, I think, today's chips have (to my mind) far too small L1's. But the cost of providing large L1s at high speeds just isn't in the cards. Most folks won't pay the price. I might. But one person won't pay them enough.

Jon



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20 Jan 2008, 7:44 pm

jonk wrote:
gamefreak wrote:
jonk wrote:
SirLogiC wrote:
I would take it by your long and very technical post that your main interest is computers right

:roll: :P :wink:
Hehe. I spent some time training on the internal design of the P-II CPU at Intel and I did chipset testing for them, for a while. I have designed some cpus, as well. And I enjoy the technology a lot. I also write a lot of software, including operating systems and compilers, though it's been 20 years since I've seriously done the compiler part.

I suppose that's a yes. ;)

Jon


If you designed the Intel P2 why didn`t you guys just put Full-Speed Cache on them like Intel did on the Celeron- 300A+. It cheaper and you get about the same performence comparing 128KB Full-Speed and 512KB Half=Speed Cache.

No, I didn't design it. I was __trained__ on its design. Different thing. I learned about the data flows, registration station, ROB, etc. About how it had already been designed by others.

In terms of cache, I can't tell you why choices were made in specific cases except to suggest that basically most everything comes down to yield/profit. The L1 caches are (were) built on the same die with the CPU. The L2 caches are connected over a separate (or were) back side bus and were on separate dies. Back in the day, anyway. Making the L1 bigger was a huge help in speed, of course, but you paid for it in terms of larger die area which meant lower yield and higher costs, which most customers wouldn't know beans about and would just buy like candy, either way. So why give them something they won't really appreciate and pay for? As shinks occurred, the clock rates increased and the die area descreased, but the smaller feature size meant far tighter control of various parameters in the manufacture. Also, larger wafer sizes give greater yield per wafer, but also lead to great difficulties in keeping uniform temperatures across the wafer during heating which either means longer processing times or better control of the heat mechanisms or else concerns about losing wafers to potato chipping or other defects. Anyway, balancing all these things in various ways, plus market analysis all gets munged together in making decisions. Some of the older CPUs had the largest L1 caches and, I think, today's chips have (to my mind) far too small L1's. But the cost of providing large L1s at high speeds just isn't in the cards. Most folks won't pay the price. I might. But one person won't pay them enough.

Jon


I`m wondering how many years of training/ Education you would need to work at Intel.



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20 Jan 2008, 7:45 pm

gamefreak wrote:
jonk wrote:
gamefreak wrote:
jonk wrote:
SirLogiC wrote:
I would take it by your long and very technical post that your main interest is computers right

:roll: :P :wink:
Hehe. I spent some time training on the internal design of the P-II CPU at Intel and I did chipset testing for them, for a while. I have designed some cpus, as well. And I enjoy the technology a lot. I also write a lot of software, including operating systems and compilers, though it's been 20 years since I've seriously done the compiler part.

I suppose that's a yes. ;)

Jon


If you designed the Intel P2 why didn`t you guys just put Full-Speed Cache on them like Intel did on the Celeron- 300A+. It cheaper and you get about the same performence comparing 128KB Full-Speed and 512KB Half=Speed Cache.

No, I didn't design it. I was __trained__ on its design. Different thing. I learned about the data flows, registration station, ROB, etc. About how it had already been designed by others.

In terms of cache, I can't tell you why choices were made in specific cases except to suggest that basically most everything comes down to yield/profit. The L1 caches are (were) built on the same die with the CPU. The L2 caches are connected over a separate (or were) back side bus and were on separate dies. Back in the day, anyway. Making the L1 bigger was a huge help in speed, of course, but you paid for it in terms of larger die area which meant lower yield and higher costs, which most customers wouldn't know beans about and would just buy like candy, either way. So why give them something they won't really appreciate and pay for? As shinks occurred, the clock rates increased and the die area descreased, but the smaller feature size meant far tighter control of various parameters in the manufacture. Also, larger wafer sizes give greater yield per wafer, but also lead to great difficulties in keeping uniform temperatures across the wafer during heating which either means longer processing times or better control of the heat mechanisms or else concerns about losing wafers to potato chipping or other defects. Anyway, balancing all these things in various ways, plus market analysis all gets munged together in making decisions. Some of the older CPUs had the largest L1 caches and, I think, today's chips have (to my mind) far too small L1's. But the cost of providing large L1s at high speeds just isn't in the cards. Most folks won't pay the price. I might. But one person won't pay them enough.

Jon


I`m wondering how many years of training/ Education you would need to work at Intel.


I am figuring a lot...

though i think it would be so fun working there...


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jonk
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20 Jan 2008, 8:07 pm

gamefreak wrote:
I`m wondering how many years of training/ Education you would need to work at Intel.
Depends on the job. In my case, chipset testing, you do need a few skills to begin with.

Jon



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20 Jan 2008, 8:10 pm

jonk wrote:
gamefreak wrote:
I`m wondering how many years of training/ Education you would need to work at Intel.
Depends on the job. In my case, chipset testing, you do need a few skills to begin with.

Jon


what about in cleanroom fabrication?


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jonk
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20 Jan 2008, 8:12 pm

Strapples wrote:
gamefreak wrote:
I`m wondering how many years of training/ Education you would need to work at Intel.
I am figuring a lot...

though i think it would be so fun working there...
I really enjoyed the chance to learn more about how the processors are designed, internally, how signals and data are routed, about updating buggy processor instructions in the field, and how they test these things before they commit them to expensive runs of silicon. A different side of things, so to speak. I also got a chance to talk with BIOS writers from Phoenix (which Intel owns 50% of, I think, or did at some time, anyway.) I probably have been through BIOS listings about as much as most. Anyway, yes, I found it educational and enjoyed that.

Jon



jonk
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20 Jan 2008, 8:18 pm

Strapples wrote:
jonk wrote:
gamefreak wrote:
I`m wondering how many years of training/ Education you would need to work at Intel.
Depends on the job. In my case, chipset testing, you do need a few skills to begin with.

Jon


what about in cleanroom fabrication?
I have been in there, in a bunny suit. And I've worked on designing and programming some of the instrumentation used in FABs -- mainly non-contact means of measuring in-situ temperatures in real time on the wafers in rapid thermal processing units. But I haven't actually had a production job in the fab, so I don't know what the range of required education might be for the various jobs there. I suspect that some of them are fairly simple and do not need a lot of knowledge. I've met a few in production and certainly some of them were not all that highly educated. So I would guess that at the lower end of things, not much is needed.

Jon